Central Signal Processor Consortium Report – SKA eNews – July 2015

Design of the SKA Central Signal Processing (CSP) Element

Who are we?

The Central Signal Processor (CSP) Consortium is comprised of 16 signatories from 9 countries with more than 10 additional participating organisations. The Consortium includes a rich mixture of engineers, scientists and managers from various academic institutions, industry and government labs spread over 5 continents (see https://www.skatelescope.org/csp/ for more details). As might be expected, it has been a challenge to proceed efficiently with such a diverse and distributed team.

The lead organisation of the Consortium is the National Research Council of Canada (NRC). NRC has contracted MDA Systems Ltd. (MDA) to assist in leading the Consortium. The Science and Technology Facilities Council (STFC) and Astronomy Technology Centre (ATC) are providing Consortium leadership in the Quality Assurance and Systems Engineering disciplines.

What are we designing?

The CSP Element includes design of the hardware and associated firmware/software necessary for the generation of visibilities, pulsar survey candidates and pulsar timing data from the telescope arrays. The CSP is the central processing “brain” of the SKA.  The imaging processor converts the digitised signals from the SKA receivers into the form used by the Science Data Processor to make detailed images of astrophysical phenomena. The non-imaging processors survey the sky for new pulsars and produce high-precision timing observations of known pulsars.

Prior to the rebaselining announcement in March 2015, the CSP Consortium had been designing the central processor for all three telescopes (SKA-low, SKA-mid, and SURVEY). The CSP Element had been divided into sub-elements: a correlator for SKA-low and SURVEY each, a correlator beamformer for SKA-mid, a Pulsar Search Engine and Pulsar Timing Engine for SKA-mid, local monitoring and control-clock-timing.

Current Status of Design Activities

Stage1: PDR Review

During Stage 1 the team performed requirements analysis and review of the Level 1 requirements, functional analysis and design decomposition to Level 2 and 3. Level 2 and 3 requirement specifications were developed by making assumptions where there were gaps or ambiguities at Level 1. Candidate technologies were explored with early prototyping, analysis and simulation. External and internal interface control documents (ICDs) were created between the CSP and other elements and within the sub-elements of the CSP. Physical implementation proposals (preliminary designs) were submitted for the sub-elements, in some cases, multiple competing proposals were submitted based on different technologies and architectures. A Preliminary Design Review (PDR) was held for the CSP in December 2014 to review the significant design package, resulting in useful feedback from the review panel to the design teams regarding areas to explore further and with the mandate to downselect technologies (and teams) as quickly as possible to allow better focus of resources leading to the Critical Design Review (CDR).

Stage 2: Rebaselining and Downselection

Since the PDR, the Consortium has been addressing actions from the review, progressing the technology and team downselects, and coming to grips with the rebaselining implications. It has been a struggle for the Consortium to reconfigure resources as a result of rebaselining scope reductions coupled with downselections but progress is being made. The New Zealand Alliance (led by AUT, with support from a number of organisations such as Open Parallel), who had been leading the Survey Correlator sub-element, now will need to be re-allocated, along with others such as CSIRO. However, these skills and resources offered by these teams will be effectively utilised in the design of the remaining sub-elements.

First Uniboard2 delivered at the beginning of May using the latest FPGA technology from Altera

The technology downselects are on-going and are equally challenging due to a number of viable technologies being promoted with national and geo-political factors at play and questions about technology availability and freeze dates. The goal for the consortium is to complete this re-alignment and proceed to a Delta PDR in July 2015 with a more focussed solution and effective team. This is a period of transition for the Consortium.

In the meantime, the sub-element design teams have continued to progress into detailed design and prototyping with the most promising architectures and technologies. There has also been much activity on the system engineering side (requirements, ICDs, test planning, modeling, processes) with contributions from SKA South Africa, Reutech Radar Systems, STFC UK ATC, New Zealand Alliance, Oxford, NRC, Swinburne, and MDA.

Key Sub-element Design Development

Local Monitoring and Control (LMC) and Clock and Timing

The CSP Local Monitoring and Control (LMC) sub-element is responsible for coordinating all the CSP processing functions according to commands from the Telescope Manager (TM), returning status rolled-up from the various processing sub-elements, and configuring and sequencing the sub-elements. This sub-element is being led by NRC with assistance from NCRA and INAF. There are on-going discussions with SKAO about adjusting the split of LMC capability between TM and CSP. The design of the clock and timing capability required by the processing sub-elements has been led by Selex ES.

MID Correlator and Beamformer (Mid.CBF)

Redback-4 Systems for ASKAP

There are three competing solutions for the Mid.CBF. NRC, with international support, has produced a design based on the PowerMX specification (www.powermx.org) using FPGAs. CSIRO has produced a design based on the ASKAP Redback FPGA architecture and SKA SA based on the MeerKAT SKARAB FPGA architecture. Although all solutions are based on FPGAs to minimise power consumption there are key differences in the designs that have led to vigorous debates amongst the experts. Although all designers would like to carry their designs further the Consortium will have to decide on one primary solution shortly in order to proceed to CDR.

LOW Correlator and Beamformer (Low.CBF)

As a result of an ECP (Engineering Change Proposal), the low correlator will be expanded for a beamformer to be supported for the additional Non-imaging Processing. There are a number of possible solutions for the Low.CBF but only the correlator has been studied thus far. With Oxford leading, together with ASTRON (and partners including JIVE), STFC (UK ATC and RAL), CSIRO and INAF, the team has focussed on FPGA-based solutions that could be on one of several platforms, namely Uniboard2, PowerMX, or Redback. In addition, Curtin/ICRAR has led a group to study a COTS hardware GPU-based software solution including contributions from CISCO, NVIDIA, NCRA, and ASTRON. This solution is likely to be used as a backup and perhaps for early integration activities with the FPGA solution being the primary.

Pulsar Search Engine

The Pulsar Search Engine is the largest of the sub-elements. Initially it was designed for SKA-mid only but is now being extended to support SKA-low as well. The design team is lead by University of Manchester with support from Oxford and the Max Plank Institute. There are many trade-offs available within the Pulsar Search processing algorithms that are being explored to balance the processing required, and thus power consumed, against the effectiveness and speed of the search for pulsars. A very scalable architecture has been promoted that allows for easy deployment of the same architecture for the two sites and telescopes. Much effort will be expended going forward to optimize the design to minimize power consumption and development and capital cost. COTS hardware with GPUs is the baseline technology but various accelerator options are being considered.

Pulsar Search Engine Compute Node

Pulsar Timing Engine

The Pulsar Timing Engine is a smaller sub-element that will perform high-fidelity, high-precision timing observations of known pulsars. Swinburne University is leading a design based on COTS hardware with GPU accelerators; an early version of this solution will be commissioned at the MeerKAT telescope in 2015.

Path to CDR

Overall, the CSP Consortium has made great progress since November 2013 and is well positioned to proceed effectively to CDR in late 2016. The focus will be on prototyping for risk reduction and detailed design of the downselected solutions in preparation for procurement in the next phase. There are still many challenges ahead but we are confident we will pull together and get the work done.

Part of the CSP Consortium and SKAO at Technical Interchange Meeting #4 at SKA SA, Cape Town