Central Signal Processor

 

What do we mean when we refer to Central Signal Processor (CSP) in the SKA design?

CSP LOGO

The “Central Signal Processor” (CSP) element includes design of the hardware and associated firmware/software necessary for the generation of visibilities, pulsar survey candidates and pulsar timing from the telescope arrays. CSP does not include the buildings, cooling, shielding or power supply to the building. CSP does include the distribution of data within the processor, diagnostic tools etc necessary for the maintenance and operation of the system.

We have assembled the world experts and the best minds in this domain to tackle this ‘grand signal processing problem’“, says David Stevens, CSP Project Manager. “Our multi-national consortium, spread over 5 continents, will work collaboratively to ‘crack this nut’ enabling this new instrument to transform our understanding of the universe. I’m really looking forward to working with this dynamic and talented team.

More about the CSP
The CSP is the central processing “brain” of the SKA.  It converts digitised astronomical signals detected by SKA receivers (antenna & dipole -“rabbit-ear”- arrays) into the vital information needed by the Science Data Processor to make detailed images of deep space astronomical phenomena that the SKA is observing.  It will also design a “non-image processor” in order to facilitate the most comprehensive and ambitious survey yet to find new pulsars and precisely time known pulsars.

Pulsars are rapidly rotating dead stars the size of a small city that allow astronomers to probe the conditions of extreme gravity (the volume of 1 sugar cube of a pulsar is as massive as a mountain!), as well as act as distant beacons in an international effort to detect gravitational waves, predicted by Einstein to be emitted by orbiting super-massive objects engaged in a death spiral.

Circuit boards and racks in the JVLA correlator.  Credit: Brent Carlson

Circuit boards in the JVLA correlator.  Credit: Brent Carlson

The CSP Technology
The CSP will utilise the latest generations of high-speed digital processing chips, high-speed/high-capacity memory chips, high-capacity fibre communications, high-speed circuit boards, high-speed modelling software and electronic test equipment, and the latest in agile, robust, and intelligent software.

JVLA Correlator

Racks in the JVLA correlator.  Credit: Brent Carlson

The main CSP Challenge
The challenge with the CSP is that it must process enormous amounts of real-time data, and in so doing produce enormous amounts of output to be consumed by the Science Data Processor. It will be located in remote locations and must be designed to deliver the maximum science possible within a hard cost cap and an aggressive timeline.

The CSP Consortium
The CSP Consortium is comprised of a diverse group of highly skilled and motivated individuals within organisations that have agreed to work together in a spirit of collaboration and competition to design the CSP Element for the SKA Telescope. With representation from more than 25 organisations located in 12 countries on 5 continents, the Consortium includes a rich mixture of scientists, engineers, managers, and technicians from various academia institutions, industry and government labs.

Collectively, the Consortium has direct experience in the specification, design, implementation, fielding, operation and support of correlators for all existing major radio telescopes, including SKA pre-cursors (ASKAP, MeerKAT, MWA) as well as the JVLA (Jansky Very Large Array), LOFAR (Low-Frequency Array for Radioastronomy), ALMA (Atacama Large Millimeter/submillimeter Array), VLBI (Very Long Baseline Interferometry) arrays and others. Similarly, the Consortium has world-leading experience in some 7 generations of pulsar instrumentation including detection and timing.

The Redback-3 digital processing board used in the Australian SKA Pathfinder (ASKAP), illustrating one of the hardware architectures being considered for  the SKA. The board has six Field Programmable Gate Arrays, 12 DRAM and communication capacity of 360 Gbs. Credit: CSIRO

The Redback-3 digital processing board used in the Australian SKA Pathfinder (ASKAP), illustrating one of the hardware architectures being considered for  the SKA.
The board has six Field Programmable Gate Arrays, 12 DRAM and communication capacity of 360 Gbs. Credit: CSIRO

As would be expected from such a diverse group, there is a broad range of experience with respect to standards used during development. Several standards including ISO-9001 and various military, space, telecom, and commercial standards will be used.

The lead organisation of the Consortium is the National Research Council of Canada (NRC). NRC has contracted MDA Corporation (MDA) to provide project management and engineering services to assist in leading the Consortium. Two groups from within the Science and Technology Facilities Council (STFC) of the UK, UK ATC (Astronomy Technology Centre) and RAL (Rutherford Appleton Laboratory), are joining NRC and MDA to provide Consortium leadership in the Quality Assurance and Systems Engineering discipline.

The CSP Consortium is led by David Loop of NRC in Canada.

 

Institutions involved in the CSP Consortium include:

Contact information of people involved at each institution can be provided by the consortium Project Manager David Stevens

Click on the Map below to find out more about partners involved in the Central Signal Processor consortium

SKA Global Consortia

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